The present invention relates to improving the switching performance of an integrated circuit, and more particularly to a logic circuit employing clocked differential cascode voltage switch logic with precharging circuitry.
Pass transistor logic is one of the oldest logic techniques used in forming integrated circuits. Prior to the advent of complementary metal-oxide semiconductor (CMOS) technology currently popular in integrated circuit fabrication, pass transistor logic had been used in n-channel metal-oxide semiconductor (NMOS) circuits. Pass transistor logic was subsequently implemented in CMOS technology circuits. For example, CMOS pass transistor logic has been applied in microprocessors and other circuits. Comparisons have been made between pass transistor logic and standard CMOS logic for a variety of different applications and power supply voltages.
Static pass transistor logic circuits of the type shown in FIGS. 1-2 have been used in CMOS technology and integrated circuits. For example, static pass transistor CMOS circuits have been widely used in the design of microprocessors. However, static pass transistor logic circuits suffer from a common problem: there is a threshold voltage drop at the input across a pass transistor. As illustrated in FIG. 1, if the input voltage source 28 is VDD at a logical xe2x80x9c1xe2x80x9d or high logic state, then the voltage at a node 34 (the input to the inverter 22) will rise only to VDD-VTN, where VTN is the threshold voltage of the transistor 26. In addition, the rise time required for the node 34 to reach this voltage (VDD-VTN) is theoretically infinite, since the NMOS pass transistor 26 has a final state which theoretically has infinite resistance.
This problem is exacerbated if, as shown in FIG. 2, the output of one pass transistor 32 is used to drive the gate of another transistor 26. In the circuit shown in FIG. 2, the voltage at node 34 (the input to the inverter 22) will charge only to VDD-2VTN. This result is unacceptable in low power supply circuits and therefore design rules preclude such a configuration.
Various techniques have been used to overcome these problems. One technique is the use of level restore circuits, examples of which are illustrated in FIGS. 3-4. Referring to FIG. 3, a level restore circuit 30 is illustrated, including a pass transistor 26 and level restore transistor 38, in which the output of the inverter 22 is fed back to control a PMOS level restore transistor 38. If the input to the inverter 22 at the node 34 is switching high, then the output of the inverter 22 is switching low, thus driving the gate of the PMOS level restore transistor 38 to pull up the input to the inverter 22 at the node 34. This is a positive feedback circuit which tends to latch the input high regardless of how slowly the original input signal was rising. In this manner, the level restore circuit 30 overcomes the threshold voltage drop at the input to the inverter 22. The level restore circuit 40 shown in FIG. 4 is essentially equivalent to the level restore circuit 30 of FIG. 3.
Another problem plaguing pass transistor logic circuits is noise. Concerns about the noise resilience of pass transistor logic spurred the development of complementary pass transistor logic. FIGS. 5-7 show various implementations of complementary pass transistor logic with different types of buffer circuits. FIG. 5 illustrates simple inverter-type buffers 22 used for power gain. FIG. 6 shows cross-coupled level restore buffers 62, 64. The cross-coupling insures a full voltage swing at the inputs to the inverters 22. FIG. 7 shows a silicon-on-insulator (SOI) implementation of cross-coupling for a CMOS pass transistor logic circuit.
Another approach to the noise problem uses the differential cascode voltage switch (DCVS) logic illustrated in FIGS. 8-9. The DCVS logic circuit shown in FIG. 8 uses cross coupling to provide a full voltage swing at the output of the pass transistor logic circuit. A more efficient realization is achieved by using a combination of complementary pass transistor logic (102, 104) and DCVS logic as shown in FIG. 9.
While cross-coupling such as that shown in FIGS. 8-9 serves to reduce the effect of threshold voltage drops, it is not entirely effective in reducing the effect of threshold voltage drops on switching speed. The bulk of the problem occurs during the low to high transition at the output of the pass transistor logic circuit 102, 104. Because of the voltage drop in the transistors 102, 104 attempting to pull the output high, this output rises slowly.
Accordingly, there is a strong desire and need to improve the switching performance of integrated circuits using logic that overcomes the voltage drop, noise and switching speed problems of pass transistor logic.
A logic circuit and associated method are provided to improve the switching performance of integrated circuit devices. Complementary pass transistor logic and differential cascode voltage switch (DCVS) logic are combined with precharge circuitry, and the output nodes of the pass transistor circuits are precharged high. The precharging avoids slow transition times and can significantly increase the performance of switching in integrated circuits.
The logic circuit includes first and second complementary control logic circuits (e.g., pass transistor circuits), first and second capacitors each having one plate connected to a first potential and another plate connected to a respective one of first and second complementary outputs of said logic circuit, a differential cascode voltage switch circuit, comprising at least first and second transistors each having gates cross-coupled to said first and second complementary outputs, and precharge circuitry configured to precharge said first and second complementary outputs to a desired (e.g., high) state.
In another aspect of the invention, switching performance is improved by allowing only fast high to low transitions at the output of the pass transistor circuits. The outputs of the complementary pass transistor circuits are both precharged high. If the output of the pass transistor logic is attempting to switch high, then the output will simply remain high at the precharged state. If the output of the pass transistor logic is attempting to switch low, then it will do so quickly through low resistance NMOS transistors in the pass transistor circuits.
In another aspect of the invention, clocking transistors are used to assist in precharging the outputs of the circuit. The gate of each clocking transistor is controlled by a clocking signal which has a first state (e.g., low) during a precharge phase and then transitions to a second state (e.g., high) during an operation phase. During the precharge phase, the outputs of the circuit are precharged high and de-coupled from the pass transistor logic circuits. During the subsequent operation phase, precharging ceases and the outputs of the circuit are coupled to the pass transistor logic circuits. The output of the circuit is evaluated during the operation phase.